1. Field of the Invention
The present invention is related to a voltage monitoring apparatus which monitors a d.c. voltage and detects a condition of an apparatus from a change in the voltage. The present invention is appropriately applied to a technique for detecting a condition of a power source voltage of a drive circuit device which drives a power device and for accordingly controlling the device, for example.
2. Description of the Background Art
FIG. 8 is a block diagram showing one example of a conventional voltage monitoring circuit. FIGS. 9A to 9E are timing charts showing an operation of the circuit which is shown in FIG. 8.
In the voltage monitoring apparatus which is shown in FIG. 8, a certain voltage set value VL and a voltage set value VH which is higher than the voltage set value VL are alternately set as the level of a reference voltage signal V6 so that a hysteresis operation is performed and a condition of an external apparatus to the voltage monitoring apparatus is accordingly controlled. When a d.c. voltage input signal INP drops lower than the voltage set value VL, the apparatus detects a drop in the d.c. voltage and provides an external apparatus which uses the d.c. voltage as a power source voltage with a detect signal FOP which is indicative of an abnormal condition of the power source voltage. In this case, the voltage monitoring apparatus maintains a current condition in response to an instantaneous drop such as a power source noise (without outputting the detect signal FOP). The voltage monitoring apparatus outputs the detect signal FOP which detects a voltage drop in a d.c. power source only when such a condition continues that the d.c. voltage input signal INP becomes lower than the voltage set value VL only during a certain period of time or longer. Further, outputting the detect signal FOP, the voltage monitoring apparatus executes a hysteresis operation that the detect signal FOP will not be outputted in a normal condition unless the d.c. voltage input signal INP rises up to the voltage set value VH.
First, in FIGS. 8 and 9A to 9E, in a normal condition, a reference voltage generating circuit 6P outputs a reference voltage signal V6P which has the voltage set value VL which is low. A comparison circuit 2P compares a d.c. voltage of the d.c. voltage input signal INP with the voltage set value VL of the reference voltage signal V6P. In this case, since the d.c. voltage of the d.c. voltage input signal INP is higher than the voltage set value VL, the comparison circuit 2P outputs an output signal 2P having an L level. An integrating circuit 3P is in a state of integrating in a negative direction, when the comparison circuit 2P outputs an output signal N2P which has the L level, and therefore, is constant with the minimum potential and outputs an output signal V3P which has the minimum level. The output signal V3P from the integrating circuit 3P is supplied to one input terminal of a comparison circuit 4P. The comparison circuit 4P is a comparison element with a voltage set value V2P at the other input terminal of the comparison circuit 4P, and is formed by a comparator or an inverter whose threshold value is V2P. When a level of the output signal V3P from the integrating circuit 3P is then minimum potential, since the level of the output signal V3P is lower than the voltage set value V2P, the comparison circuit 4P outputs an output signal N4P which has an H level. In accordance with a result of the output signal N4P from the comparison circuit 4P, a control circuit 5P outputs a control signal N5P which allows the voltage generating circuit 6P to output the voltage set value VL. As a result, until a level of the d.c. voltage input signal INP becomes equal to or lower than the voltage set value VL, a current normal operation is maintained. At this stage, the level of the detect signal FOP is the H level.
In a condition where the d.c. voltage level of the d.c. voltage input signal INP drops, an output from the voltage generating circuit 6P is the reference voltage signal V6P which has the voltage set value VL which is low. When the d.c. voltage level of the d.c. voltage input signal INP becomes lower than the voltage set value VL, the comparison circuit 2P outputs the output signal N2P which has the H level. As a result, the integrating circuit 3P enters a state of integrating in a positive direction upon receipt of the output signal N2P which has the H level from the comparison circuit 2P, and a potential of the output signal V3P outputted from the integrating circuit 3P starts to increase. The output signal V3P outputted from the integrating circuit 3P is compared with the voltage set value V2P outputted from the comparison circuit 4P, and from a point of time at which the level of the output signal V3P becomes equal to or larger than the voltage set value V2P, a portion composed of the integrating circuit 3P and the comparrison ciruit 4P serves as a timer circuit. If the level of the d.c. voltage input signal INP exceeds the set value VL of the comparison circuit 2P before the output signal V3P outputted from the integrating circuit 3P becomes equal to the voltage set value V2P outputted from the comparison circuit 4P, the comparison circuit 2P outputs the output signal N2P which has the L level, and therefore, the integrating circuit 3P is reset so that the output signal V3P returns to the minimum level again. Hence, the value to which the reference voltage signal V6P is set remains the set value VL.
Conversely, when the level of the d.c. voltage input signal INP becomes lower than the set value VL over a period of time which is set by the timer circuit described above, through the operation described above, the output signal V3P from the integrating circuit 3P becomes higher than the voltage set value V2P outputted from the comparison circuit 4P, so that the comparison circuit 4P outputs the output signal N4P which has the L level. When the output signal N4P from the comparison circuit 4P becomes the L level, the control circuit 5P outputs the control signal N5P which allows the voltage generating circuit 6P to set an output voltage from the voltage generating circuit 6P to the set value VH. It then follows that the comparison circuit 2P compares against the voltage set value VH which is high. This condition is maintained until the level of the d.c. voltage input signal INP becomes equal to or larger than the voltage set value VH. At this stage, the level of the detect signal FOP is the L level.
As can be understood from the foregoing, this apparatus functions as a hysteresis circuit which operates in response to a change amounting to or over the threshold value which is determined by the voltage set values VH and VL of the comparison circuit 2P and a change amounting to or over a time which is determined by an integrating coefficient and the voltage set value V2P, and outputs the detect signal FOP to outside.
The invention described in Japanese Patent Application Laid-Open Gazette No. 63-313077 discloses to form a timer circuit with an RC integrating circuit and a comparator with a hysteresis characteristic, which is formed by a Schmidt circuit whose one of input terminals is connected to its output terminal, and discloses a circuit which monitors a level of an input d.c. power source. Meanwhile, the invention described in Japanese Patent Application Laid-Open Gazette No. 63-315963 discloses a comparator circuit which has a hysteresis characteristic and a timer circuit portion which is connected to an output terminal of the comparator circuit.
However, in a conventional voltage monitoring circuit as that shown in FIGS. 8 and 9A to 9E which comprises a timer circuit which filters out a variation in an inputted d.c. voltage while using a time which is determined by an integrating coefficient of an integrating circuit and one set voltage of a comparator, the following problems have been addressed.
FIGS. 10A to 10E show operation timing of the circuit shown in FIG. 8 which has problems. A case is assumed where the d.c. voltage input signal INP varies beyond or below the set value VL in approximately the same cycle as a time which is determined by the integrating circuit 3P and the set value V2P of the comparison circuit 4P as shown in FIGS. 10A to 10C. In such a case, although the comparison circuit 4P outputs the H-level output signal N4P which has a short duration time, if the duration time of the output signal N4P is equal to or shorter than a time (response width) in which the elements of the control circuit 5P and the voltage generating circuit 6P are responsive, since the voltage generating circuit 6P can not change the set value VL to the high potential set value VH, the voltage monitoring apparatus itself repeats the same operation. On the other hand, when the logic of the control circuit 5P for creating the detect signal is responsive during the duration of the H level of the output signal N4P of the comparison circuit 4P, the detect signal FOP changes to the L level in synchronization to the cycle of the d.c. voltage input signal INP. As a result, the detect signal FOP chatters or oscillates. However, although the detect signal FOP externally indicates a drop in the d.c. voltage, as an internal operation of the voltage monitoring apparatus, a hysteresis operation is not indicated which corresponds to such a drop in the power source voltage. Hence, this disagreement adversely affects an external circuit which operates in accordance with the condition of the detect signal FOP.
Thus, in the conventional voltage monitoring apparatus, since delayed responses of the elements which form the voltage monitoring apparatus are not considered at all, although the apparatus can not invoke a hysteresis operation as the elements can not follow a change in the inputted d.c. voltage due to the delayed responses, the detect signal alone chatters, so that the change in the apparatus may be transmitted to outside the apparatus.